The speed at which microprocessors can execute instructions has increased dramatically in recent years. The increase in speed has been so great that propagation delays in data travelling to and from the microprocessor chip have become a limitation on processor performance.
As an example, the 8080 microprocessor, which was introduced around 1973, commonly operated at a clock speed of 1 MegaHerz (MHz). Each instruction requires between 3 and 5 clock cycles, giving a resulting speed of approximately 200,000 to 300,000 instructions per second. In contrast, a processor of the '486 family, available in 1991, can have a clock rate of 50 MHz. A typical instruction requires about 2.5 clock cycles, resulting in a speed of about 20 million instructions per second. Plainly, this speed is about 100 times faster than that of the 8080 processor.
In order to reduce propagation delays between the microprocessor and associated memory components, developers have devised ways to pack large numbers of ICs onto small carriers. One such carrier is the Multi-Chip Module, or MCM, shown in FIG. 1. The MCM is a multi-layered structure, in which conductors 3 interweave among themselves to interconnect between the ICs and external traces 6. The interweaving can be explained by reference to FIG. 2. Different layers 9 and 12 carry different patterns 15 and 18 of conductors 20. When the layers are assembled, vias 21 connect the patterns, and the assembly provides a 3-dimensional interwoven connection system, which allows any arbitrary point A to connect with any other arbitrary point B, as indicated by dashed path D.
Several types of MCM are in use. One type is constructed of multi-layered printed-circuit boards. The conductive patterns are printed using silk-screen techniques, and have a line width limit of about 0.005 inches (i.e., about 5 mils). (The limit refers to a minimum width of lines: the narrowest line possible is 5 mils. Line width is inversely proportional to interconnect density. The lines are referred to as interconnects, and narrower lines allow more of them to be packed into a given space, thus increasing the density, measured in number of lines per square inch.)
With such a large line width, the density of lines is small, compared to that available in other approaches, as will be seen. However, the cost is relatively low. A single, completed, pattern-bearing layer costs roughly 10 cents per square inch. A 10-layer board would thus cost about $1.00 per square inch.
A second type utilizes ceramic layers on which the patterns are printed by a silk-screen process. The line width is about 5 mils. For single layers in the form of squares about 2.times.2 inches or smaller, the price is roughly $1.00 per square inch. For larger sizes, the price increases significantly.
A third type utilizes copper polyimide layers positioned on top of ceramic layers. The printing process is photolithography, which can provide a minimum line width of less than 1 mil. However, the present cost is roughly $32 per square inch for a four-layer unit.
A fourth type uses silicon layers, with photolithographic printing. The line width can be less than 1 mil, and the cost is about $15 per layer, totaling about $60 for four layers.
The cost estimates given above are approximate, and can vary greatly, depending on numerous factors, such as quantity purchased, previous dealings between the parties, and complexity of the conductor patterns.
In these types of MCM, the cost increases as line width becomes smaller. Smaller line widths are required for higher IC densities. Consequently, as IC densities increase, these types of MCM will impose higher costs.